Symbol Naming Rules For Plant Model Generation In The PLC Simulation

Presented in the paper is the PLC symbol naming rules in order to simulate the virtual factory which is operated by the PLC control logic. In the PLC simulation, the corresponding model, normally called as the plant model, to the PLC receives the PLC output signal, operates virtual devices, and sends the changed PLC input signal which is updated by the virtual device movements. Therefore the plant model is necessary to verify PLC code and to simulate the virtual factory. Normally, the plant model construction takes much time and effort, requires in-depth knowledge about the simulation and PLC code, and even it might has modelling errors. To prevent the modelling error and to save the time and effort for the I/O model construction, this paper proposes the naming rules of PLC symbol to extract the necessary information. The simple example cell is applied to test the proposed approach.